ECE 437: Computer Design and Prototyping

Description

This class focused on processor design. In lab I built a single-cycle processor, then worked with a team mate to expand on it from there. This involved implementing the processor in SystemVerilog, writing test-benches for different subsystems of the processor, and writing programs to run on the processor to test its functionality, in a simulation and on an FPGA.

Key Points

Most points covered in lab were also covered in class, excluding SystemVerilog, FPGA Interfacing, and Test Benches, which were covered in a prerequisite class.

  • Lab
  • SystemVerilog
  • FPGA Interfacing
  • MIPS Instruction Set (simplified)
  • Test Benches
  • Single-Cycle Processor
  • 5 Stage Pipeline Processor
  • Register Forwarding
  • Hazard Avoidance
  • L1 Instruction and Data Caches
  • Dual-Processor
  • MSI Memory Coherency
  • Load-Link/Store-Conditional Synchronization
  • Class
  • Branch Prediction
  • Memory Consistency Models
  • Memory Coherency (beyond MSI)
  • Virtual Memory
  • Processor IO
  • DMA
  • Programmable IO
  • Carry-Look-Ahead
  • Booth's Multiplication Algorithm
  • Non-Restoring Division
  • IEEE 754 Floating-Point Arithmetic
  • Briefly Speculative Execution
  • Spectre-V1

RTL Diagram of My Single Cycle Processor